The present invention relates to CMOS imaging arrays. More particularly, the present invention relates to column readout circuits for CMOS imaging arrays and to voltage clamp circuits for column line readout circuits.
In image sensor circuit, the node voltage on the floating diffusion node drops with increased exposure or brightness level. This voltage drop is reflected in the column voltage when the row select transistor is turned on. A clamp circuit is provided on the column line to define the lowest voltage to which the column is allowed to drop. Even though the voltage on the floating diffusion node may drop below the clamp voltage, the column is maintained at the minimum set clamp voltage thereby artificially limiting the brightness of the brightest object from which the photodiode 10 receives light energy.
The clamp circuit defines the lowest column voltage and is able to accurately limit the bright signal swing level to remain within the clipping range of the analog-to-digital converter. This prevents non-monotonic behavior in the transfer function of the sensor.
Conventional clamp circuits known to the inventors are based on open loop designs where voltage is applied from a digital-to-analog convertor (DAC) to the gate of a clamp transistor. FIG. 1 is a schematic diagram that depicts a typical pixel sensor (photodiode 10) coupled to a column line 12 for reading out the sensed light. A transfer switch 14, usually in the form of an n-channel transistor isolates the photodiode 10 from a floating node 16. The floating node 16 and the cathode of the photodiode 10 are reset to a voltage VDD on line 18 by turning on a reset transistor 20 for a reset period of time while the transfer switch 14 is turned on. After the reset time has ended, reset transistor 20 is turned off and photocharge generated by the photodiode 10 accumulates as a voltage on the capacitance of the floating node 16. At the end of an exposure period, the transfer switch 14 is turned off and the accumulated photocharge voltage is stored on the floating node 16. When it is desired to read the photocharge voltage charge out of the pixel sensor through source follower transistor 22, row select transistor 24 is turned on and the voltage representing the accumulated charge is placed on column line 12. Typically the row select transistors of all of the pixel sensors in a single row in the array of pixel sensors are all turned on at once to read out the image from an array of pixel sensors one row at a time.
A clamp circuit 26 is associated with the column line 12. The clamp circuit is provided on the column line 12 to define the lowest voltage to which the column is allowed to drop in order to prevent overexposure nonlinearities that would otherwise arise from over-ranging the analog-to-digital converter coupled to the column line. Even though the voltage on the floating diffusion node 16 may drop below the clamp voltage set by clamp circuit 26, the column line 12 is maintained at the minimum set clamp voltage to artificially control the maximum brightness of bright objects.
The column line is driven by a current source 28. The clamp circuit 26 includes a clamp transistor 30 connected across the source follower transistor 22 and the row-select transistor 24. The gate of clamp transistor 30 is driven by a voltage that is set by a voltage controller 32 in clamp circuit 26. The voltage controller 32 may contain a digital-to-analog converter 34 driven by an n-bit digital word on inputs 36. The n-bit word is set by the circuit designers to cause the clamp transistor to set a minimum voltage to which the column line 12 may drop. The clamp circuit is turned on by a global pixel readout signal (GPR) shown at reference numeral 40, activated only during image readout operations.
FIG. 2 is a voltage diagram that illustrates determination of a typical clamping level for a sample photodiode pixel sensor design. The pixel design in FIG. 2 may have a dark level of 1.9V±300 mV. The clamp transistor operates across a user variable voltage range (as set by the voltage controller 32 of FIG. 1) of between about 100 mV and 500 mV. This gives an operational signal swing of about 1.7V. At about 100 mV the clamp transistor is fully turned on and is the lowest clamp voltage to provide the necessary headroom that will maintain the bias current transistor turned on. At about 200 mV the clamp transistor turns off. This is the brightness saturation level that is set for the design. Persons of ordinary skill in the art will recognize that this example is illustrative only in order to help provide an understanding of the present invention. Such skilled persons will recognize that particular pixel sensor designs may exhibit characteristics that vary from those shown in FIG. 2 and can easily adjust column line clamping settings for particular pixel sensor and array designs from the teachings of the present invention.
The threshold voltage of the clamp transistor 30 varies with process, voltage and temperature. These variations result in precision errors in the column clamp voltage set by the clamp circuit 26. In conventional clamp circuits the column clamp voltage can vary by 250 mV or more. Such high clamp voltage variations can present a significant problem in image sensors since the bright level signal swing cannot be guaranteed to remain linear or have monotonic behavior that remains within the clipping range of the analog-to-digital converter used to convert the column output signal.
In addition, conventional column clamp circuits tend to be relatively slow and incur signal loss since they are based on open loop systems. This also presents a problem in image sensors when it is desired to operate them at frame rates suitable for video applications.